1. Field
The present disclosure relates generally to generation of test data patterns. More particularly, the disclosure relates to methods and apparatus for generating test data patterns for integrated circuits.
2. Background
Typical modern electronic circuits contain thousands or millions of individual components integrated into a single chip which are too complicated for manual testing. To test these complex electronic circuits, circuit designers are forced to rely on automated testing.
Testing can be achieved by generating test data patterns external to the chip under test and feeding the test pattern signals through the chip's input pins. Use of an external testing generator may require that the chip dedicate some of its pins for testing. This reduces the finite number of pins available for actual chip functions. Additionally, external test pattern generation may be costly, time consuming and logistically more complicated.
Chips designed to support code division multiple access (CDMA) communications are particularly complex. Typically, CDMA chips include additional signal processing functions that may not be required in other applications. To test these CDMA chips with realistic signal stimuli, the test data pattern generator would normally need to generate data patterns with comparable complex signal processing. One prior solution (for eliminating the external test generator) includes an internal test data generator circuit within the CDMA chip itself. However, this increases the complexity of the already complex CDMA chip by increasing the hardware of the CDMA chip. Another prior art solution for reducing the hardware demand of the CDMA chip is to include simplistic internal hardware that generates random test data patterns. However, this does not meet the need for testing the CDMA chip with realistic stimuli.
Accordingly, it would be desirable to generate realistic test data patterns without an external test data pattern generator and without significant increase to the CDMA chip hardware and complexity.